The integrated circuit industry relies on the continual and repeated inspection of integrated circuits as they are produced to ensure that processes are operating properly and that the integrated circuits themselves are properly formed. Automated inspection is normally the preferred method of inspection of integrated circuits. However, as integrated circuits evolve, they are becoming smaller and more complicated. Thus, there has been continual pressure to detect and classify a growing number of defects and other conditions that may be present on the substrate, but which are increasingly more difficult to see. In addition, fabrication units are producing more and more integrated circuits so as to reduce the overhead costs associated with production, and to satisfy the demands of the modern world. Such demands have resulted in a desire to reduce the time associated with integrated circuit inspection
Current inspection methods in integrated circuit manufacturing typically use two completely separate inspection tools. The first inspection tool typically inspects all of the substrate surface to identify candidate defect sites. These first inspection tools typically use optical techniques and are limited in resolution by the wavelengths of the light that they use. These first inspection tools identify many candidate defect sites, whose defect size is typically below the resolution of the optical first inspection tool used. Thus, a second higher resolution, but much slower, inspection tool is then typically used to inspect and provide high resolution images of each of the candidate defect sites. These high resolution images are then typically used to classify the defects that may or may not be found at the candidate defect sites.
The second inspection tool is typically an electron microscope. Thus, in a typical process, the integrated circuit substrate is first inspected using the first inspection tool, and then the substrate is removed from the first inspection tool and placed in the second inspection tool to further investigate the candidate defect sites, and to determine which defects identified by the first tool are those that may impact device yield. The coordinate system of the first tool must be re-acquired by the second tool, costing additional time. This may be followed by a re-inspection with the first tool with modified inspection parameters to improve its capture of these more important defects. Repeatedly transferring the substrate from the first inspection tool to the second inspection tool is time consuming, and therefore costly.
Typically, only a subset of the candidate defect sites have actual defects that negatively affect process yield. Thus, the slower second inspection tool is often bogged down by inspecting candidate defect sites that have no bearing on device yield.
What is needed, therefore, is a system for reducing the amount of handling and time needed to identify and classify those defects that impact device yield on a substrate.